1. Field of the Invention
The present invention relates to a level shifter, and more particularly, to a level shifter capable of utilizing low threshold voltage transistors or native transistors for receiving input voltages, to perform high-speed level shifting to pull high output voltage.
2. Description of the Prior Art
In general, a low voltage to high voltage level shifter is utilized for shifting a voltage level of a received signal from a low voltage level to a high voltage level, so as to shift a low voltage signal generated by a low voltage front-end element to a high voltage signal for operations of a high voltage back-end element.
For example, please refer to FIG. 1, which is a schematic diagram of a conventional level shifter 10. As shown in FIG. 1, the level shifter 10 comprises P-channel Metal oxide semiconductor Field-Effect Transistors (MOSFETs) MP1, MP2, N-channel MOSFET transistors MN1, MN2 and a buffer 100, wherein P-channel MOSFET transistors MP1, MP2 and N-channel MOSFET transistors MN1, MN2 are high voltage elements.
In short, gates of the N-channel MOSFET transistors MN1, MN2 receive input voltages IN+, IN− generated by a low voltage front-end element, respectively, and when the input voltage IN+ is high and the input voltage IN− is low, the N-channel MOSFET transistor MN1 is turned on to pull low a voltage of a gate of the P-channel MOSFET transistor MP2. Therefore, the P-channel MOSFET transistor MP2 is turned on to pull high an output voltage Vout by a system voltage VDD (i.e. the output voltage Vout is charged to a voltage level of the system voltage VDD), and inverters comprised by the buffer 100 buffer the output voltage Vout to output a high voltage signal to a high voltage back-end element. As a result, the level shifter 10 can output the high voltage signal close to the voltage level of the system voltage VDD when determining the input voltage IN+ of the low voltage signal is high.
However, with development of semiconductor processing, the input voltage IN+ of the low voltage signal level becomes lower (e.g. a high level is reduced from 1.2V to 0.9V), and threshold voltages of the N-channel MOSFET transistors MN1, MN2 are unchanged (about 0.8V), but the high voltage level of the system voltage VDD is unchanged (e.g. 3.3V). Since a difference between the high level of the input voltage IN+ and the threshold voltage of the N-channel MOSFET transistor MN1 is much small and cannot effectively pull low the gate voltage of the P-channel MOSFET transistor MP2 to pull high the output voltage Vout. Therefore, the level shifter 10 cannot be applied in high-speed level shifting, or even for performing level shifting from low voltage to high voltage. Thus, there is a need for improvement of the prior art.